IRDS lithography roadmapThe Journal of Micro/Nanopatterning, Materials, and Metrology (JM3) has appear a cardboard that outlines the lithography roadmap and the assorted challenges for the abutting 15 years.
The paper, alleged the “International Roadmap for Accessories and Systems lithography roadmap,” projects that acute ultraviolet (EUV) lithography and a next-generation adaptation will abide the capital apery options for leading-edge chips at atomic until the 0.7nm bulge in 2034. But the industry faces an array of challenges forth the way. Added apery technologies, such as absolute write, directed self-assembly (DSA) and nanoimprint, may acquisition a place. All of this could change based on a about-face in technology, amount and added factors.
The roadmap will advice adviser the lithography industry’s affairs for approaching advance and R&D. It additionally addresses the requirements, accessible options, and accepted challenges for the abutting 15 years. Mark Neisser, a lithography adept and a technology administrator for the Tan Kah Kee Innovation Laboratory at Xiamen University, is the columnist of the 2021 lithography roadmap paper. The cardboard is in the SPIE Digital Library.
The cardboard reviews and complements the lithography affiliate of the anniversary International Roadmap for Accessories and Systems (IRDS) report. The IRDS address additionally includes capacity like branch integration, metrology, CMOS, crop enhancement, and appliance benchmarking.
The antecedent of the IRDS address was the ITRS or International Technology Roadmap for Semiconductors. Between 1998 to 2015, the ITRS certificate was produced annually by experts. The ambition was to serve as the capital advertence for assorted dent and accessories technologies.
The IRDS, the almsman to the ITRS, is a set of predictions that accommodate an outline “to abridge academic, manufacturing, supply, and analysis allocation apropos the development of cyberbanking accessories and systems.” The IRDS roadmap projects approaching challenges for semiconductors and accessible solutions to those challenges. It shows that argumentation accessories will drive shrinking analytical ambit and improvements in apery for the abutting 10 years.
Lithography, the art of apery tiny appearance on chips, is analytical to accredit the development of avant-garde devices. Until 2018, chipmakers acclimated optical-based 193nm amicableness lithography accoutrement to arrangement avant-garde dent features. With assorted techniques, chipmakers continued 193nm lithography bottomward to 7nm. But at 5nm, it’s too circuitous to use these techniques.
That’s area acute ultraviolet (EUV) lithography fits in. Based on a 13.5nm wavelength, EUV lithography simplifies the apery process, enabling the abutting beachcomber of chips.
In 2018, Samsung and TSMC amid ASML’s 0.33 NA EUV scanners for use in accomplishment chips at 7nm. ASML’s EUV scanners accredit 13nm resolutions with a throughput from 135 to 145 wafers per hour (wph). Today, Samsung and TSMC are accomplishment 5nm chips application EUV. 3nm is in R&D. Samsung and SK Hynix are ramping up EUV for DRAM production. Intel and others additionally plan to accompany EUV into production.
Going forward, the IRDS lithography roadmap outlines a apparent scenario. “Extreme ultraviolet lithography (EUV) systems already in accomplishment use can boldness the aboriginal band and amplitude ambit on the roadmap if bifold apery is used. For acquaintance holes and added aperture blazon levels, bifold acknowledgment with accepted accoutrement can already boldness the minimum angle bare until ‘1.5nm’ in 2025. The ‘1.5nm’ bulge will be achievable with bifold exposure,” Neisser said in the paper.
Then, in 2025, the industry is accepted to drift to high-NA EUV, a next-generation adaptation that uses a 0.55 NA lens. The accepted EUV apparatus uses a 0.33 NA lens.
High-NA EUV is accepted to be the capital lithographic advantage for accessories until the alleged 0.7nm bulge in 2034, according to the roadmap. But there are several challenges in bringing up high-NA EUV scanners.
There are added issues. “The above lithographic challenges in the abutting 10 years are mostly accompanying to babble and defects. Bury is additionally accepted to be a challenge,” Neisser said in the paper.
Harry Levinson, editor-in-chief of the Journal of Micro/Nanopatterning, Materials, and Metrology (JM3), added: “Roadmaps such as this are invaluable for lithographers. They accredit us to accept allusive exchanges apropos technology ambit and targets that would contrarily be too company-sensitive to discuss. They additionally accommodate a accepted advertence for bodies focused on altered elements of lithographic technology–equipment, materials, masks, and metrology.”
Alternative litho techniquesThe IRDS lithography cardboard additionally addresses added alleged next-generation lithography (NGL) technologies. These accommodate DSA, direct-write lithography, and nanoimprint.
DSA isn’t a apparatus technology, per se. It’s a commutual apery access that works with added lithography systems. For example, EUV lithography could be acclimated in affiliation with DSA to accredit accomplished patterns. DSA enables patterns application block copolymers. In DSA, a lithography arrangement forms a pre-defined arrangement on a structure. The anatomy is coated with block copolymers, which again self-assemble into tiny patterns.
Controlling the defects is one of abounding challenges with DSA. That’s why DSA has added or beneath absent some drive over the years. Still, Intel continues to accompany DSA.
Meanwhile, for years, direct-write or maskless lithography was advised the ultimate apery technology. Originally developed by IBM in the 1980s, direct-write lithography makes use of an e-beam apparatus that anon patterns tiny appearance on a wafer.
Direct-write is adorable because it doesn’t crave an big-ticket photomask. But the throughputs for single-beam e-beam lithography are too slow, authoritative it too big-ticket for aggregate IC production. As a result, single-beam direct-write accoutrement are relegated to alcove applications, such as admixture semiconductors and photonics.
To break the throughput problems, the industry has been developing direct-write e-beam systems that makes use of assorted beams. But so far, the technology is still demography basis and has been relegated for alcove applications.
Nanoimprint lithography (NIL) is additionally in assorted stages of development. In the works back the 1990s, NIL resembles a backyard process. Initially, an e-beam arrangement forms a arrangement on a arrangement based on a pre-defined design. Then, a abstracted substrate is coated with a resist. The blooming arrangement is apprenticed adjoin the substrate, basic a arrangement on the substrate at affection sizes bottomward to 5nm and beyond.
The big challenges with NIL are overlay, defectivity and throughput. At the contempo SPIE Photomask EUV conference, though, Canon presented a cardboard on a nanoimprint lithography adjustment for accomplishing sub-3nm overlay. Canon has been developing a nanoimprint lithography arrangement for use in anamnesis production.
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